47th IEEE Semiconductor Interface Specialists Conference
Catamaran Hotel, San Diego, CA
December 8-10, 2016 (Tutorial: Dec 7)

Call for Late News Papers, Deadline: September 30, 2016

The SISC is a workshop-style conference that provides a forum for device engineers, solid state physicists, and materials scientists to discuss topics of common interest, formally through invited and contributed presentations, and informally during various events including two poster presentation sessions. The SISC is sponsored by the IEEE Electron Device Society, and will be held right after the IEEE IEDM.

The program includes talks and poster presentations (theory and experiment) from all areas of MOS science and technology, including but not limited to:

  • SiO2 and high-k dielectrics on Si and their interfaces
  • Insulators on high-mobility and alternative substrates (SiGe, Ge, III-V, SiC, etc.)
  • MOS gate stacks with metal gate electrodes
  • Stacked dielectrics for non-volatile memory
  • Oxide and interface structure, chemistry, defects, and passivation: theory and experiment
  • Electrical characterization, performance and reliability of MOS-based devices
  • Surface cleaning technology and impact on dielectrics and interfaces
  • Dielectrics on nanowires, nanotubes, and graphene
  • Oxide electronics and multiferroics
  • Interfaces in photovoltaics, e.g. Si passivation
  • 2D materials and devices and their interfaces

A Best Student Presentation award will be given in memory of E.H. Nicollian, who made many important contributions to the field and had a strong presence within the SISC.


Call for Late News Papers, Deadline: September 30, 2016

To submit your abstract, follow these instructions.

You can also download the 2016 Call in the PDF format. Please help us promote SISC among your colleagues and collaborators by forwarding the Call to them and by posting a hard copy at your affiliation.

For questions about the SISC focus, abstract submission, and related issues, please contact the Technical Program Chair.


2016 Confirmed Technical Invited Talks

  • Prof. K. Banerjee, UCSB
    2D/3D Tunnel FETs
  • Prof. P. McIntyre, Stanford U.
    Interface Defect Passivation for High Performance Insulator-Protected MIS Photosynthesis and Photovoltaic Cells
  • Dr. J. Muller, Fraunhofer IPMS-CNT, Dresden, Germany
    Material Innovations in Ferroelectric Hafnium Oxide - Towards Cheaper Memories, Steeper Slopes and New Value Adders for HKMG Technologies
  • Prof. J. Robinson, Penn State U.
    2D/3D Interfaces: Where the Magic Happens
  • Prof. S. Salahuddin, UC Berkeley
    Negative Capacitance and Its Implications for Low Voltage Transistors
  • Prof. S. Takagi, U. Tokyo, Japan
    Critical issues and Challenges of High-k Gate Stacks for Ge MOSFETs
  • Dr. A. Verhulst, imec, Belgium
    Perspective on III-V Tunnel-FETs: bridging the gap between ideal device design and experimental realizations through calibration
  • Prof. L.-E. Wernersson, Lund University, Sweden
    III-V Nanowire MosFETs and Tunnel FETs


2016 Wednesday Evening Tutorial

The Wednesday Evening Tutorial aims to give a good foundation in one topic frequently covered at the conference. The Tutorial is free for all SISC registered attendees.

  • Dr. T. Theis, Columbia Nano Initiative
    Materials, Devices, and Circuit Architectures for Future Electronics