The SISC is a workshop-style conference that provides a forum for device engineers, solid state physicists, and materials scientists to discuss topics of common interest both formally through invited and contributed presentations, and informally during a variety of events including a poster presentation session. The conference will be held immediately prior to the IEDM. SISC is sponsored by the IEEE Electron
The program includes talks from all areas of MOS science and technology, including but not limited to the following:
- SiO2 and high-k dielectrics on Si and their interfaces
- Insulators on high-mobility and alternative substrates (SiGe, Ge, III-V, SiC, etc.)
- MOS gate stacks with metal gate electrodes
- Stacked dielectrics for non-volatile memory
- Oxide and interface structure, chemistry, defects, and passivation: Theory and experiment
- Electrical characterization, performance and reliability of MOS-based devices
- Surface cleaning technology and impact on dielectrics and interfaces
- Dielectrics on nanowires, nanotubes, and graphene
- Oxide electronics and multiferroics
- Interfaces in photovoltaics, e.g. Si passivation
A Best Student Presentation award will be given in memory of E.H. Nicollian, who made many important contributions to the field and had a strong presence within the SISC.
2013 Technical Invited Talks
- Prof. Suman Datta, Penn State University, USA
Materials Selection and Device Design for Low Power Tunnel Transistors
- Dr. Robin Degraeve, imec, Belgium
Modeling SET and RESET transients in Hf-based RRAM devices using the Hourglass approach
- Dr. Thanasis Dimoulas, NCSR DEMOKRITOS, Greece
Growth and characterization of silicene and germanene
- Prof. Debdeep Jena, University of Notre Dame, USA
SymFET: A novel Graphene-Insulator-Graphene Tunneling Device
- Prof. Yasuyuki Miyamoto, Tokyo University of Technology, Japan
Heavily doped epitaxially grown source in InGaAs MOSFET for high drain current density
- Prof. Krishna Saraswat, Stanford University, USA
Low Resistance MIS Contacts to Ge and III-V Devices
- Prof. Susanne Stemmer, University of California at Santa Barbara, USA
Reducing EOT and Interface Trap Densities of High-k/III-V Gate Stacks
- Prof. Eric Vogel, Georgia Institute of Technology, USA
Frequency Dispersion in CV plots of MOS Devices on III-V Substrates:
Disorder-Induced Gap States or Border Traps
2013 Wednesday Evening Tutorial
The Wednesday Evening Tutorial aims to give a good foundation in one topic frequently covered at the conference. The Tutorial is free for all SISC registered attendees.
- Prof. Michelle Simmons, The University of New South Wales, Australia
The development of a quantum computer in silicon
Down-scaling has been the leading paradigm of the semiconductor industry since the invention of the first transistor in 1947. However miniaturization will soon reach the ultimate limit, set by the discreteness of matter, leading to intensified research in alternative approaches for creating logic devices. One of the most exciting of these is quantum computation. We will present devices that address the ultimate limit of device miniaturization in silicon where we have patterned dopants in a crystalline environment with atomic precision to act as one dimensional leads, single electron transistors and control gates. In particular we demonstrate precision single atom transistors and spin-read-out in a silicon quantum computing architecture that is inherently scalable. We will discuss the benefits of donors as qubits and address some of the challenges to achieving truly atomically precise devices in all three spatial dimensions.
Abstract submission deadline is July 22, 2013
To submit your abstract, follow these instructions.
You can also download the Call in the PDF format. Please help us promote SISC among your colleagues and collaborators by forwarding the Call to them and by posting a hard copy at your affiliation.
For questions about the SISC focus, abstract submission, and related issues, please contact the Technical Program Chair.